Maker Faire Bay Area 2024
Verilog Meetup - Get into FPGA Programmable Logic and Learn How the Chips are Designed
Home: California, United States
“Verilog, ASIC, FPGA” are not exactly household words, but they are at the very heart of the microelectronics revolution that brought us smartphones, fast internet, 3D graphics and AI acceleration. For the last 40 years, the Verilog hardware description language has been used to design the logic of chips. An ASIC (Application Specific Integrated Circuit) is the chip itself, and an FPGA (Field Programmable Gate Array) is a chip used to prototype an ASIC. Verilog Meetup is a community that meets every Sunday at Hacker Dojo in Mountain View, California, and over Zoom - with participants on all continents. We create Verilog examples used by more than 25 universities worldwide. We run seminars, help to prepare for job interviews, and explore new chip design methodologies.
https://verilog-meetup.com/
Makers
Verilog Meetup
Verilog Meetups are attended by three groups of people: 1. A core team of hardware engineers meeting in Silicon Valley who drive the development of the open projects. 2. Beginners who are directed to become proficient in Verilog and join the core group. 3. People around the globe who join the meetings online and help to prepare seminars overseas.
https://verilog-meetup.com/
What Inspired You to Make This?
The professional engineers who started Verilog Meetup noticed and decided to solve three challenges in hardware design education: 1. Barrier to entry to the field. Building digital circuits at the Register Transfer Level (RTL) is similar to programming, but uses different building blocks: finite state machines and pipelines, instead of software loops and function calls. By making design techniques accessible, we enable people to create new mixes of hardware and software for AI, space electronics, and other things that have not yet been invented. 2. The gap between Academia and Industry. Many students coming to job interviews are not trained to solve microarchitectural problems common in modern CPU, GPU, networking, and AI. We are trying to collect the best open industrial practices and convert them into educational materials to make beginning engineers more productive faster. 3. EDA and FPGA vendor lock. The examples we develop support more than 30 boards with FPGAs from Xilinx, Altera, Gowin, and Lattice and aim to be compatible with open-source ASIC design tools. Our example framework gives more flexibility to university professors who want to concentrate on teaching the students the hardware design rather than vendor-specific details and who want to be able to quickly switch to another vendor based on their student project needs.
